Superconducting Heater Cryotron-Based Reconfigurable Logic Towards Cryogenic IC Camouflaging

Superconducting electronics are among the most promising alternatives to conventional CMOS technology thanks to the ultra-fast speed and ultra-high energy efficiency of the superconducting devices. Having a cryogenic control processor is also a crucial requirement for scaling the existing quantum computers up to thousands of qubits. Despite showing outstanding speed and energy efficiency, Josephson junction-based circuits suffer from several challenges such as flux trapping leading to limited scalability, difficulty in driving high impedances, and so on. Three-terminal cryotron devices have been proposed to solve these issues which can drive high impedances (>100 k{\Omega}) and are free from any flux trapping issue. In this work, we develop a reconfigurable logic circuit using a heater cryotron (hTron). In conventional approaches, the number of devices to perform a logic operation typically increases with the number of inputs. However, here, we demonstrate a single hTron device-based logic circuit that can be reconfigured to perform 1-input copy and NOT, 2-input AND and OR, and 3-input majority logic operations by choosing suitable biasing conditions. Consequently, we can perform any processing task with a much smaller number of devices. Also, since we can perform different logic operations with the same circuit (same layout), we can develop a camouflaged system where all the logic gates will have the same layout. Therefore, this proposed circuit will ensure enhanced hardware security against reverse engineering attacks.Comment: 12 pages, 5 figure

Machine Learning-powered Compact Modeling of Stochastic Electronic Devices using Mixture Density Networks

The relentless pursuit of miniaturization and performance enhancement in electronic devices has led to a fundamental challenge in the field of circuit design and simulation: how to accurately account for the inherent stochastic nature of certain devices. While conventional deterministic models have served as indispensable tools for circuit designers, they fall short when it comes to capture the subtle yet critical variability exhibited by many electronic components. In this paper, we present an innovative approach that transcends the limitations of traditional modeling techniques by harnessing the power of machine learning, specifically Mixture Density Networks (MDNs), to faithfully represent and simulate the stochastic behavior of electronic devices. We demonstrate our approach to model heater cryotrons, where the model is able to capture the stochastic switching dynamics observed in the experiment. Our model shows 0.82% mean absolute error for switching probability. This paper marks a significant step forward in the quest for accurate and versatile compact models, poised to drive innovation in the realm of electronic circuits

Multiplexed gradient descent: Fast online training of modern datasets on hardware neural networks without backpropagation

We present multiplexed gradient descent (MGD), a gradient descent framework designed to easily train analog or digital neural networks in hardware. MGD utilizes zero-order optimization techniques for online training of hardware neural networks. We demonstrate its ability to train neural networks on modern machine learning datasets, including CIFAR-10 and Fashion-MNIST, and compare its performance to backpropagation. Assuming realistic timescales and hardware parameters, our results indicate that these optimization techniques can train a network on emerging hardware platforms orders of magnitude faster than the wall-clock time of training via backpropagation on a standard GPU, even in the presence of imperfect weight updates or device-to-device variations in the hardware. We additionally describe how it can be applied to existing hardware as part of chip-in-the-loop training, or integrated directly at the hardware level. Crucially, the MGD framework is highly flexible, and its gradient descent process can be optimized to compensate for specific hardware limitations such as slow parameter-update speeds or limited input bandwidth

The thermally-coupled imager: A scalable readout architecture for superconducting nanowire single photon detectors

Although superconducting nanowire single-photon detectors (SNSPDs) are a promising technology for quantum optics, metrology, and astronomy, they currently lack a readout architecture that is scalable to the megapixel regime and beyond. In this work, we have designed and demonstrated such an architecture for SNSPDs, called the thermally-coupled imager (TCI). The TCI uses a combination of time-of-flight delay lines and thermal coupling to create a scalable architecture that can scale to large array sizes, allows neighboring detectors to operate independently, and requires only four microwave readout lines to operate no matter the size of the array. We give an overview of how the architecture functions, and demonstrate a proof-of-concept $32\times32$ imaging array. The array was able to image a free-space focused spot at 373 nm, count at 9.6 Mcps, and resolve photon location with greater than 99.83\% distinguishability